.::Cache Mapping Algorithm::.

Each cache has its own dedicated Translation Lookaside Buffer (TLB) to convert linear addresses to physical addresses.

Data Cache:

• 4-way set associative, 64-entry TLB for 4KB pages.
• Separate 4-way set associative, 8-entry TLB for 4MB pages.

Code Cache:

• One 4-way set associative, 32-entry TLB for 4KB pages.