.::Pipelining::.

The Pentium uses a 5 stage pipeline:

• Fetch
• Decode Stage 1
• Decode Stage 2
• Execute
• Write Back

Example Timing Diagrams

The Pentium also uses a Dynamic Branch Prediction

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Fetch

• The fetch stage gets the next instruction from memory and puts it into the prefetch buffer once the previous instruction has been consumed. It is kept there until used.
  

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Decode Stage 1

• The decode stage 1 takes the first 3 bytes from the prefetch buffer. These 3 bytes contain the required information to know what to do. If needed the decode stage 1 sends the rest of the instruction to the decode stage 2.
  

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Decode Stage 2

• The decode stage 2 expands the opcode and sends control signals to the ALU if needed. It also controls the computation of the complex addressing modes.
  

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Execute

• The execute stage does the ALU operation and updates any registers.
  

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Write Back

• The write back stage if needed, updates registers and flags and updates memory.
  

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Examples Timing Diagrams

• Timing Diagram With Out Pipelining:
  
  
  • It takes 15 time cycles for three instructions.
• Timing Diagram With Pipelining:
  
  
  • It takes seven time cycles for three instructions.

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Branch Prediction

• The Pentium uses a dynamic branch prediction scheme. They have an algorithm that uses past branches to predict if the branch will be taken or not.
  

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