.::Cache Replacement::.

• Replacement in the Pentium is handled by an LRU mechanism with 1 bit per set.
• Replacement in the Pentium with MMX is handled by a pseudo LRU mechanism with 3 bits per set.
• When a line must be replaced, the cache will first select which of 10:11 and 12:13 was least recently used.
• Then the cache will determine which of the two lines was least recently used and mark it for replacement.