.::Cache Write Policy::.
Replacement in the Pentium is handled by an LRU mechanism with 1 bit per set.
Writeback or writethrough on a line by line basis.
Follows MESI protocol.
Method of providing cache coherency.
M (modified) – the line has been modified; the memory copy is invalid.
E (exclusive) – the cache has the only copy of the data; the memory is valid.
S (shared) – more than one cache is holding a copy of this line; the memory copy is valid.
I (invalid) – this cache line is not valid
Inherently write protected since it only holds instructions.
As a result, supports a subset of MESI – shared and invalid states only.