Power PC G5
Team 2: Gerson Paiz-Escobar | Victor Roman | Phillip Busche
POWER stands for Power Optimization With Enhanced RISC and is the main processor in many IBM servers, workstations, and supercomputers of single-chip performance today.
The PC in PowerPC stands for performance computing. Descended from the POWER architecture, it was introduced in 1993. It was designed from the beginning to run on a broad range of machines, from battery-operated handhelds to supercomputers and mainframes. But it saw its first commercial use on the desktop, in the Power Macintosh 6100.
Born of an alliance between Apple, IBM, and Motorola (also known as the AIM alliance), the PowerPC was based on POWER, but with a number of differences. For instance, PowerPC is open-endian, supporting both big-endian and little-endian memory models, where POWER had been big-endian. The original PowerPC design also focused on floating-point performance and multiprocessing capabilities. Still, it did and still does include most of the POWER instructions. Many applications work on both, perhaps with a recompile to make the transition.
PowerPC is based on the POWER Architecture designed by Motorola. A collaboration
by IBM, Apple, and Motorola has made this RISC chip very successful.
Virtual address range: 64 bits, or 18exabites
Physical address range: 42 bits or 4 terabytes
64 bit data path and registers
Native support of 32-bit application code
64K L1 instruction cache; 32K L1 data cache, parity protected
512 internal L2 cache
General purpose registers (GPRs)
Floating point registers (FPRs)
Special purpose registers (SPRs)
Give status and control of resources within the core.
SPRs that can be read and written include:
Count register, Link register, Integer exception register
Three register files, each holding 32 architected values and 48 rename registers
Addressable Memory -[back to top]
The G5 processor fully supports Big-Endian mode and has limited support with Little-Endian mode based on implementation.
The move to 64-bit processing results in a similarly dramatic leap in the amount of memory supported. Computers keep track of data stored in memory using memory addresses. A memory address is a special kind of integer, which points to one byte in memory. Since memory addresses are computed in 64-bit registers capable of expressing 18 billion billion integers, the PowerPC G5 can theoretically address 18 exabytes (18 billion billion bytes) of virtual memory. In practice, memory addressing is defined by the physical address space of the processor. The PowerPC G5, with 42 bits of physical address space, supports a colossal 242 bytes, or 4 terabytes, of system memory. Although it’s not currently feasible to purchase 4 terabytes of RAM, the advanced architecture of this processor allows for plenty of growth in the future.
Supports signed and unsigned numbers
Defines two different binary fixed-length format
IEEE Operations -[back to top]
Instruction Format -[back to top]
All instructions in the PowerPC are 32-bit long and follow
a regular format.
For all load/store, arithmetic, and logical instructions,
the opcode is followed by two 5-bit register references, enabling 32 general-purpose
registers to be used.
Addressing Modes -[back to top]
PowerPC uses a simple and relatively straightforward set of addressing
The PowerPC provides two alternative addressing modes for load/store instructions: indirect addressing and indirect indexed addressing.
Indirect Addressing: the instruction includes a 16-bit displacement to be added to a base register, which may be any of the general-purpose registers. In addition, the instruction may specify that the newly computed effective address is to be fed back to the base register, updating the current contents. The update option is useful for progressive indexing of arrays in loops.
Indirect Indexed Addressing: the instruction references a base register and an index register, both which may be any of the general-purpose registers. The effective address is the sum of the contents of these two registers.
Three branch addressing address modes are provides: Absolute addressing, Relative addressing and Indirect addressing.
Absolute Addressing: when is used with unconditional branch instructions,
the effective address of the next instruction is derived from a 24-bit
immediate value within the instruction. The 24-bit value is extended to
a 32-bit value by adding two zeros to its least significant end and sing
extending. For conditional branch instructions, the effective address
of the next instruction is derived from a 16-bit
Relative Addressing: the 24-bit immediate value (unconditional branch) or 14-bit immediate value (conditional branch) is extended as before. The resulting value is then added to the program counter to define a location relative to the current instruction.
Indirect Addressing: is the other conditional branch addressing, this
mode obtains the effective address of the next instruction from either
the link register or the counter register.
Instruction Set -[back to top]
The PowerPC provides a large collection of operations types.
For integer arithmetic, all operand must be contained either in registers
or as part of the instruction. With register addressing, a source or destination
operand is specified as one of the general-purpose registers. With immediate
addressing, a source operand appears as a 16-bit signed quantity in the
Data Size: data can be transferred in units of byte, halfword, word,
Data Types Supported -[back to top]
The PowerPC can deal with data types of 8 (byte), 16 (halfword), 32 (word), and (doubleword) bits length. Some instructions required that memory operands be aligned on a 32-bit boundary. In general, however alignment is not required. One interesting feature of the PowerPC is that can use either little-endian or big-endian style. The processor interprets the contents of a given item or data depending on the instruction. The fixed-point processor recognizes the following data types:
Unsigned byte: used for logical or integer arithmetic operations. It
is loaded from memory into a general register by zero extending on the
left to the full register size.
In addition, the PowerPC supports the single and double precision floating point data types defined in IEEE 754.
Source: Computer Organization & Architecture by William Stallings
Pipelining -[back to top]
Fetch - The PowerPC G5 anticipates the need for data and instructions and pre-fetches them into its large L1 and L2 caches.
To protect the integrity of data and instructions, L1 cache is parity-protected and L2 cache is protected using Error Correction Code (ECC) logic.
Fetch & Decode - A low-latency 512K L2 cache provides fast access to data and instructions—at rates up to 64 GBps. Instructions are fetched from the L2 cache into a direct-mapped 64K L1 instruction cache. At the same time, 32K of write-through, two-way associative L1 data cache can fetch up to eight active data streams simultaneously.
Up to eight instructions per clock cycle are fetched from the L1 instruction cache for decoding.
Highly accurate dynamic prediction - Up to 2 branches per cycle, 98% accuracy
Note: Decoding divides each instruction into smaller sub-operations, giving the processor more freedom to schedule execution of code in parallel.
Multiple pipelined execution units, branch prediction, and a SIMD, or
vector processing (Altivec) unit.
With each clock cycle, up to eight instructions can be fetched from the direct-mapped 64K L1 instruction cache
32K of write-through, two-way associative L1 data cache can fetch up to eight active data streams, which are loaded into data registers behind the execution units
Different types of instructions are processed concurrently by the execution units, which include two floating-point units, two integer units, two load/store units, a condition register unit, a branch prediction unit, and a vector processing unit
Refer to Figure 1 for details.
Uses a “RISC-like” hardwired implementation.
Inside the processor - Milli-coded instructions are decoded into simpler instructions . During each clock cycle the PowerPC microprocessor can send a group of five simpler instructions into its execution units.
These instructions are broken down into similar groups for instruction execution, memory slots 0-3 are reserved for micro-instructions.
Most micro-operations occupy slots 0 to 3 in the processor.
When the entire group of micro-instructions is executed, and all preceding groups are also executed, the processor writes down the final results and the Group Completion Table gets cleared.
A Group Completion Table indicates the maximum size of a continuous instruction block (as if cut out of the program) that can be processed by the processor at a given moment
To be exact, this is the maximum number of processed micro-instructions, which the instructions from the continuous part of the program are translated into.
Note: The Group Completion Table size will be increased if the processor has a long pipeline.
Interconnections -[back to top]
Frontside Bus Up To 1.25GHz:
Sources for Pipelining, Interconnections, and Microprogramming:
Memory -[back to top]
The PowerPC G5 128-bit memory controller supports fast 400MHz, DDR SDRAM
-synchronous dynamic random access memory.
Eight DIMM slots, and can hold up to 8GB of DDR memory, which is ahead
of it’s time.
Buyers Note: Typically a PowerPC G5 has 512 MB standard.
Cache -[back to top]
Has two L1 and one L2 memory caches.
L2 Cache 512K 8-way Associative
Virtual Memory -[back to top]
Each program can access 264 bytes of “effective Address (EA) space.
Sources for Memory, Cache, and Virtual Memory:
Apple – Power Mac G5 - Architecture. http://www.apple.com/powermac/architecture.html.