Load, Store, Prefetch, Load Store Unsigned Byte, Swap, and Compare and Swap are the only instructions that access memory. All of the instructions except Compare and Swap use either two r registers or an r register and simm13 to calculate a 64-bit byte memoryaddress. Compare and Swap uses a single r register to specify a 64-bit byte memoryaddress. To this 64-bit address, the IU appends an ASI that encodes address space information.

The destination field of a memory reference instruction specifies the r or f register(s) that supply the data for a store or receive the data from a load or LDSTUB. For SWAP, the destination register identifies the r register to be exchanged atomically with the calculated memory location. For Compare and Swap, an r register is specified whose value is compared with the value in memory at the computed address. If the values are equal, the destination field specifies the r register that is to be exchanged atomically with the addressed memory location. If the values are unequal, the destination field specifies the r register that is to receive the value at the addressed memory location; in this case, the addressed memory location remains unchanged.

The destination field of a PREFETCH instruction is used to encode the type of the prefetch. Integer load and store instructions support byte (8-bit), halfword (16-bit), word (32-bit), and doubleword (64-bit) accesses. Floating-point load and store instructions support word, doubleword, and quadword memory accesses. LDSTUB accesses bytes, SWAP accesseswords, and CAS accesses words or doublewords. PREFETCH accesses at least 64 bytes.