The SPARC V9 architecture uses big-endian byte order by default; the address of a quadword, doubleword, word, or halfword is the address of its most significant byte. Increasing the address means decreasing the significance of the unit being accessed. All instruction accesses are performed using big-endian byte order. The SPARC V9 architecture also can support little-endian byte order for data accesses only; the address of a quadword, doubleword, word, or halfword is the address of its least significant byte. Increasing the address means increasing the significance of the unit being accessed.Integer Unit Memory Alignment Requirements
Halfword accesses are aligned on 2-byte boundaries; word accesses (which include instruction fetches) are aligned on 4-byte boundaries; extended-word and doubleword accesses are aligned on 8-byte boundaries. An improperly aligned address in a load, store, or load-store instruction causes a trap to occur, with possible exceptions. Programming Note – By setting i = 1 and rs1 = 0, you can access any location in the lowest or highest 4 KB of an address space without using a register to hold part of the address.FP/VIS Memory Alignment Requirements
Extended word and doubleword (64-bit) accesses must be aligned on 8-byte boundaries, quadword accesses must be aligned on 16-byte boundaries, and Block load (BLD) and Block store (BST) accesses must be aligned on 64-byte boundaries. All references are 32, 64, or 128 bits. They must be naturally aligned to their data width in memory except for double-precision floating-point values, which may be aligned on word boundaries. However, if so aligned, doubleword loads/stores may not be used to access them, resulting in less efficient and nonatomic accesses. An improperly aligned address in a load, store, or load-store instruction causes a mem_address_not_aligned exception to occur, with the following exceptions:
The processor uses big-endian byte order for all instruction accesses and, by default, for data accesses. It is possible to access data in little-endian format by using load and store alternate instructions that support little-endian data structures. It is also possible to change the default byte order for implicit data accesses.Address Space Identifiers
Versions of load/store instructions, the load and store alternate instructions, can specify an 8-bit address space identifier (ASI) to go along with the load/store data instruction. The load and store alternate instructions have three sources of ASIs:
Load and store instructions provide an implicit ASI value of ASI_PRIMARY, ASI_PRIMARY_LITTLE, ASI_NUCLEUS, or ASI_NUCLEUS_LITTLE. Load and store alternate instructions provide an explicit ASI, specified by the imm_asi instruction field when i = 0, or the contents of the ASI register when i = 1.Privileged and Non-privileged ASIs
ASIs 0016 through 7F16 are restricted; only privileged software is allowed to access them. An attempt to access a restricted ASI by non-privileged software results in a privileged_action exception. ASIs 8016 through FF16 are unrestricted; software is allowed to access them whether the processor is operating in privileged or non-privileged mode.