Group 3 Presentation :: UltraSPARC IV

Cache Mapping Algorithms

Data CacheThe Data Cache (D-cache) is virtual-indexed, physical-tagged (VIPT). Virtual addresses are used to index into the cache tag and data arrays while accessing the D-MMU, (i.e. D-TLBs). The resulting tag is compared against the translated physical address to determine cache hit. A side-effect inherent in a virtual-indexed cache is address aliasing.
Instruction CacheIt is physically indexed and physically tagged and never contains modified data.
Write Cache
Prefetch Cache It is physically indexed and physically tagged and never contains modified data.

L2-Cache

CODE EXAMPLE 10-2 reflects the cache replacement algorithm when all 4 ways of the
L2-cache are active.
CODE EXAMPLE 10-2 L2-cache Replacement Policy
module lfsr (rand_out, event_in, reset, clk);
	output [3:0] rand_out;
	input event_in;
	input reset;
	input clk;
wire [4:0] lfsr_reg;
dffe #(5) ff_lfsr (lfsr_reg, lfsr_in, ~reset, event_in, clk);
// 01010 is the non-reachable state for this implementation.
wire [4:0] lfsr_in = {~lfsr_reg[0],
		lfsr_reg[0] ^ lfsr_reg[4],
		lfsr_reg[3],
		lfsr_reg[0] ^ lfsr_reg[2],
		lfsr_reg[0] ^ lfsr_reg[1]};
// update on reads that miss the L2-cache
assign event_in = ec_lt_cs_r_d1 & ~ec_lt_we_r_d1 &
~lt_ec_hit_miss_d1;

dffire #(5) f_lfsr (lfsr_reg, lfsr_in, reset, event_in, clk);

assign rand_out = { lfsr_reg[1] & lfsr_reg[0],
		lfsr_reg[1] & ~lfsr_reg[0],
		~lfsr_reg[1] & lfsr_reg[0],
		~lfsr_reg[1] & ~lfsr_reg[0]};
endmodule