IBM S/390 Architecture

Group 6

Team: Richard Brown, Pierre Fontenelle, Kristofor Jacobson, Yue Liu
  1. Overview/History of Architecture
  2. ALU/CPU
  3. Control Unit

ALU/CPU Registers5

Current instruction information for the active process is kept in the PSW (Program Status Word) register. The PSW contains information regarding CPU state and the current instruction. Interrupt processing on the S/390 is handled by swapping values into and out of the PSW. Fixed locations in physical memory store PSW values for various types of system interrupts, similar to the implementation of an interrupt vector table on Intel x86 architecture.

Instructions fall into the following categories: general, decimal, floating point support (FPS), binary floating point (BFP), hexadecimal floating point (HFP), control and I/O.

There are 16 general-purpose registers for integer and decimal arithmetic and logical operations or accumulation; 15 of them are also available for memory addressing. These registers are 64 bits in length. The general-purpose registers can be combined in pairs for some operations that require a 128-bit operand. Pairs of general-purpose registers are little endian, with the lower order 64 bits residing in an odd-numbered register (e.g., 0-1, 2-3, 4-5, etc.). Therefore, all pairs of general-purpose registers begin with, and are referenced by, an even-numbered register.

Fifteen of the general-purpose integer registers can be used to store an address base or index. The PSW is a specialized address register in that it stores the instruction pointer, but it also contains data not related to instruction address.

The S/390 also has 16 floating point registers that are 64 bits in length. The floating point registers can also be combined in pairs when a 128-bit operand is required; however, the registers are paired differently. Pairs of floating point registers are always either both even or both odd-numbered registers (e.g., 0-2, 1-3, 2-4, 3-5, etc.).

Sixteen registers are available specifically for control functions; these registers are 64 bits in length.

Additionally, sixteen registers are available that are designated "access registers" and are used for memory access. These registers are 32 bits in length, and are used differently depending on the mode of the CPU.

Addressable Memory

The architecture of the IBM S/390 was until recently based on "ESA/390", or "Extended System Architecture/390". ESA/390 had 31-bit addressable memory space, or a total of 2 gigabytes. The new IBM S/390 architecture, named "z/Architecture", is currently capable of addressing 256 gigabytes of main memory storage, but is software limited to addressing 128 gigabytes. To support legacy systems, the current "z/Architecture" S/390 can run in legacy 31- and 24-bit modes to support ancestors of the current S/3906.

Physical or "Real" memory is mapped by the S/390 operating system using a virtual memory management process. Physical and virtual memory are actually accessed in 4096 byte blocks; the virtual blocks are "pages" while the physical blocks are called "frames."

Memory access on the modern S/390 is the joint responsibility of several system components. The virtual storage manager (VSM) manages the mapping between a process running in the system and real (physical) or auxiliary (disk) storage. Real/physical memory is managed by the real storage manager (RSM); the auxiliary storage manager (ASM) manages access to disk storage. The system resource manager (SRM) is responsible for controlling access to various addressable storage areas; the SRM is what determines if infrequently requested physical memory pages can be swapped to auxiliary storage to free up fast physical memory, and also handles page faults when they occur.

The instruction set includes memory load and store functions that treat the memory as either little- or big-endian. Instructions are also available for converting values already loaded from memory from little- to big-endian and vice-versa.

Integer Representation

Floating Point Representation

Instruction Formats7

An instruction on the IBM S/390 is constructed of two major components: the opcode and the operands. Instructions on the S/390 vary in length, ranging from one halfword (16 bits) to three halfwords (48 bits), containting variable opcode and operand lengths. Based on the halfword standard for instructions, it is necessary that they be located in storage (memory) on halfword boundaries. They follow one of 18 basic formats: E, I, RR, RRE, RRF, RX, RXE, RXF, RS, RSE, RSL, RSI, RI, RIL, SI, S, SSE, and SS, with three variations of RRF, two of RS, RIL, and four of SS. These format names will be further explained, but first we will discuss operand formats to make things clearer.

Operands may be in three formats: operand values located in registers, operand values located in storage (memory), and immediate value operands. In the case of some instructions as we will see, some operands are implicit and are not contained within the instruction.

There are 16 general registers which are useable by instructions. These registers may function as base-address or index registers for indirect addressing, as well as accumulators for ALU arithmetic. Registers are 32-bit in length, and are identified by numbers 0 through 15. The "R field" of an instruction is a 4-bit section of the instruction designated to identifying which of the 16 registers is used. There may be more than one R field in an instruction. Registers also may be implicitly used, depending on a particular opcode.

Operands stored in memory may have an implied length. They may also be specified by a bit-mask. The "L field" of an instruction may be either 4-bits or 8-bits in length. Its length may also be specified by the contents of one of the 16 general registers. Memory address operands are not stored as exact address location, but rather an offset implementation is used. Benefits of this approach include:

The address used to refer to storage either is contained in a register designated by the R field in the instruction or is calculated from a base address, index, and displacement, specified by the B, X, and D fields, respectively, in the instruction.

Immediate operands are located in the "I field" of an instruction, which may be 8-bits, 16-bits, or 32 bits in length. The binary value stored in the I field is the actual operand value; there is no value retrieval from storage (memory) or registers.

We now will explain the format names for the different formats of instructions.

Which instruction format used is determined by the first two bits of an instruction. They are as follows:

Addressing Modes

The S/390 has two modes when it comes to accessing storage (memory). These modes are:

Which mode to use is determined by the status of bit 32 of the Program Status Word (PSW). If bit 32 is set to 0, 24-bit addressing is used, and if it is set to 1, 31-bit addressing is used. In both modes, instruction addresses are wrapped around, where the instruction at address 2x-2 is followed by the instruction at address 0, where x is 24 or 31, whichever mode is set.

In a given instruction accessing storage (memory), the operand address may be found either in the R field of the instruction, or the accumulated value of base, index, and displacement values, which are all stored in general purpose registers and are considered the B, X, and D fields of an instruction respectively. The base and index values are 32-bit length, and the displacement value has a 12-bit length.

The value generated is only an intermediate value, and is still not the final address. Regardless of which address mode is currently enabled, bit 0 of this intermediate value is always ignored, and set to 0 for the actual operand address. In 24-bit addressing mode, bits 1-7 are also ignored and set to 0 for the actual operand address, and bits 8-31 of the intermediate value are bits 8-31 of the actual operand address. In 31-bit addressing mode, bits 1-31 of the intermediate value are bits 1-31 of the actual operand value.

Instruction Sets

Instructions executed by the CPU fall into any of 7 categories. These categories are:

Data Types Supported

The CPU supports a variety of data types. These include integers, booleans, characters, floating points, and coded decimals.

Integers, Booleans, and Characters, namely binary data have instructions for arithmetic, branching, comparing, conversions, loading, mov, shift, store, test, translate and packing/unpacking.

Floating Points, both in BFP and HFP formats, have instructions for basic arithmetic, add, subtract, multiply, divide, as well as square root, store, load, compare, and convert data.

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