UltraSPARC IV

Presentation Group 3:
David Walker, Ryan Jean, & Trent Pack

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Table of Contents:

1. Overview/history of architecture
2. ALU/CPU
   • ALU/CPU Registers
     • MAR, MBR, ACC, etc.
     • Specialized Registers
     • Standard Registers
     • Flag Register
   • Addressable Memory
   • Integer Representation
   • Floating Point Representation
   • Instruction Formats
   • Addressing Modes
   • Instruction Set
     • Data Transfer Instructions
     • Data Manipulation Instructions
       • Arithmetic/logic instructions
       • Shift/rotate instructions
       • Comparison instructions
       • Special purpose instructions
     • Program Manipulation Instructions
     • Status Management Instructions
   • Data Types Supported
     • Identify level of support, i.e. instructions available for that data type
3. Control Unit
   • Pipelining
   • Microprogramming
4. Interconnection Structure(s)
5. Memory
   • CPU memory/registers/scratchpads/etc
   • Cache
   • Types
   • Mapping Algorithm
   • Replacement Policy
   • Write Policy
   • Virtual Memory
   • Logical Address Space
   • Hardware/OS Support
   • Mapping Algorithm
   • Replacement Policy
   • External Memory
   • How supported

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Sources:
http://sunsolve.sun.com/pub-cgi/show.pl?target=content/content8
http://bwrc.eecs.berkeley.edu/CIC/archive/cpu_history.html
http://www.sun.com/processors/manuals/USIV_v1.0.pdf
http://www.sun.com/processors/manuals/USIIIv2.pdf
http://www.sparc.com/standards/SPARCV9.pdf